Peripheral interface circuit for an I/O node of a computer system
US6725297B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2002 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Oct 16, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/128
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A peripheral interface circuit for an I/O node of a computer system. A peripheral interface circuit for an input/output node of a computer system includes a first buffer circuit, a second buffer circuit and a bus interface circuit. The first buffer circuit receives packet commands and may include a first plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels. The second buffer circuit is coupled to receive packet commands from the bus interface circuit and may include a second plurality of buffers each corresponding to a respective virtual channel of the plurality of virtual channels. The bus interface circuit may be configured to translate selected packet commands stored in the first buffer circuit into commands suitable for transmission on a peripheral bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.