Method and apparatus for combining architectures with logic option
US6725316B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 18, 2000 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Mar 27, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is provided for selecting one of a plurality of data bus width configurations of a memory device using a logic circuit. The logic circuit includes a plurality of I/O circuits each connected to at least one of a plurality of memory arrays, and at least one address selection data path connected to at least one of the I/O circuits. A signal transmitted on the address selection data path selects one of a plurality of arrays from which to access data for each I/O circuit. When in a larger bus width configuration, each of the I/O circuits is connected to a data bus line. When in a smaller bus width configuration, a subset of the I/O circuits is connected to the data bus line and data from the plurality of memory arrays is output through the subset of I/O circuits, which selectively switch outputs between memory array inputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.