Laterally diffused MOS transistor (LDMOS) and method of making same
US6727127B1 · kind B1 · utility
12Cited by
3References
11Claims
0Family size
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Key dates
| Filing date | Nov 21, 2002 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Nov 21, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
Abstract
An improved laterally diffused MOS (LDMOS) transistor architecture is provided by using a nitride cap on a gate structure and forming a spacer around the gate structure and then self-aligning a source contact and drain contact with a gate by using the same mask for source and drain dopant implantation and for silicide formation with all source and drain areas being silicided. The reduced source/drain on resistance (Rdson), shorter distance from channel to source contact, and better gate oxide integrity improves operating linearity, increases Ft and GM and reduces the drift in Idq and Rdson.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.