Method of forming local interconnects
US6727168B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 24, 2001 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Oct 24, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A first dielectric layer is formed over a first transistor gate and a second transistor source/drain region. Contact openings are formed in the first dielectric layer to the first transistor gate and to the second transistor source/drain region. A second dielectric layer is formed over the first dielectric layer and to within the contact openings. The second dielectric layer is etched selectively relative to the first dielectric layer to form at least a portion of a local interconnect outline within the second dielectric layer to extend between the first transistor gate and the second transistor source/drain region. The etching removes at least some of the second dielectric layer within the contact openings. Conductive material is formed within the local interconnect outline within the second dielectric layer which electrically connects the first transistor gate with the second transistor source/drain region. Other aspects are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.