Patent · US Expired

Method for on-chip testing of memory cells of an integrated memory circuit

US6728147B2 · kind B2 · utility

2Cited by

3References

12Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Peter Beer · Waldshut-Tiengen, DE
Jochen Kallscheuer · Birkenfeld, DE
Gunnar Krause · Munich, DE

Key dates

Filing date	Jul 24, 2002
Grant date	Apr 27, 2004
Priority date	—
Expiry date	Jul 24, 2022

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/10
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for on-chip testing of memory cells of a cell array of an integrated memory circuit includes writing different data patterns to memory cells and reading the different data patterns from the memory cells in order to test the memory cells. A basic data pattern is stored in a data word register and read out by applying a data control signal provided by a controller. In addition to the basic data pattern, at least one further data pattern, which differs from the basic data pattern and is stored in a data word register section, is accessed in a targeted manner through the use of the data control signal. As a result the test proceeds rapidly and yields extensive test information.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.