Peter Beer
40Patents
7h-index
20Co-inventors
61Inventor score
Filing activity: Dec 18, 2000 → Aug 29, 2008
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7231562B2 | Memory module, test system and method for testing one or a plurality of memory modules | Physics | 145 | Expired |
| US6612738B2 | Method for determining the temperature of a semiconductor chip and semiconductor chip with temperature measuring configuration | Physics | 23 | Expired |
| US6829185B2 | Method for precharging memory cells of a dynamic semiconductor memory during power-up and semiconductor memory | Physics | 19 | Expired |
| US6756787B2 | Integrated circuit having a current measuring unit | Physics | 14 | Expired |
| US7038956B2 | Apparatus and method for reading out defect information items from an integrated chip | Physics | 13 | Expired |
| US6671221B2 | Semiconductor chip with trimmable oscillator | Physics | 11 | Expired |
| US7137049B2 | Method and apparatus for masking known fails during memory tests readouts | Physics | 8 | Expired |
| US7088612B2 | MRAM with vertical storage element in two layer-arrangement and field sensor | Physics | 7 | Expired |
| US7302622B2 | Integrated memory having a test circuit for functional testing of the memory | Physics | 5 | Expired |
| US6657452B2 | Configuration for measurement of internal voltages of an integrated semiconductor apparatus | Physics | 5 | Expired |
| US6670665B2 | Memory module with improved electrical properties | Electricity | 4 | Expired |
| US7159156B2 | Memory chip with test logic taking into consideration the address of a redundant word line and method for testing a memory chip | Physics | 4 | Expired |
| US6737695B2 | Memory module having a memory cell and method for fabricating the memory module | Electricity | 4 | Expired |
| US6639861B2 | Integrated memory and method for testing an integrated memory | Physics | 3 | Expired |
| US6858447B2 | Method for testing semiconductor chips | Physics | 3 | Expired |
| US7107501B2 | Test device, test system and method for testing a memory circuit | Physics | 3 | Expired |
| US6891431B2 | Integrated semiconductor circuit configuration | Physics | 3 | Expired |
| US6740917B2 | Integrated semiconductor memory fabrication method | Electricity | 3 | Expired |
| US7197678B2 | Test circuit and method for testing an integrated memory circuit | Physics | 3 | Expired |
| US6728147B2 | Method for on-chip testing of memory cells of an integrated memory circuit | Physics | 2 | Expired |
| US6754110B2 | Evaluation circuit for a DRAM | Physics | 2 | Expired |
| US6831320B2 | Memory cell configuration for a DRAM memory with a contact bit terminal for two trench capacitors of different rows | Electricity | 2 | Expired |
| US7205596B2 | Adiabatic rotational switching memory element including a ferromagnetic decoupling layer | Electricity | 2 | Expired |
| US7490274B2 | Method and apparatus for masking known fails during memory tests readouts | Physics | 2 | Active |
| US6862234B2 | Method and test circuit for testing a dynamic memory circuit | Physics | 2 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.