Stackable semiconductor package and method for manufacturing same
US6730544B1 · kind B1 · utility
167Cited by
25References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 13, 2000 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | Oct 26, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18301
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stackable semiconductor package having a lead frame, a plurality of electrical paths, and a sealing material. The leadframe has a plurality of leads, each one of the plurality of leads having a top portion exposed to a top surface of the semiconductor package and a bottom portion resting flush with a bottom surface of the semiconductor package. In this manner, the leads extending from the top surface to the bottom surface of the semiconductor package provide an electrical path for connecting and electrically powering a second semiconductor package stacked on top of a first bottom semiconductor package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.