Structure of flash memory device and fabrication method thereof
US6730959B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2002 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | Oct 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A flash memory device includes a substrate having a trench, a deep N-type well region in the substrate, a stacked gate structure on the substrate, a first and a second spacer on a sidewall of the stacked gate, wherein the first spacer is connected with the top of the trench, a source region in the substrate under the first spacer, a drain region in the substrate under the second spacer, a P-type well region between the stacked gate and the deep N-type well region, wherein the junction between the two well regions is higher than the bottom of the trench, a doped region along the bottom and the sidewall of the trench, wherein this doped region is connected with the source region and isolates the P-type well region from the contact formed in the trench, the contact being electrically connected to the source region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.