Semiconductor integrated circuit device with vertically stacked conductor interconnections
US6731007B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2000 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | Aug 13, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor integrated circuit device, upon connection of an interconnection made of aluminum or aluminum alloy and another interconnection made of Cu or Cu alloy, a barrier conductor film or plug is disposed at the joint portion between these interconnections. Among the interconnection layers, the uppermost one is made of a wiring material such as aluminum or aluminum alloy, while the lower one is made of Cu or Cu alloy. The lowest interconnection is made of a conductive material other than Cu or Cu alloy. For example, the conductive material which permits minute processing and has both low resistance and high EM resistance such as tungsten is employed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.