Chip testing within a multi-chip semiconductor package
US6732304B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 21, 2000 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | Jan 24, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method is provided for testing a secondary chip housed within a multi-chip packaged semiconductor device. The packaged semiconductor device includes a secondary chip and a primary chip, with the secondary chip communicating with the primary chip through signal drivers. The secondary chip also includes at least one test signal driver connected to the signal drivers and to certain external connectors that may be shared with the primary chip. The test signal drivers provide testing of the secondary chip using standard integrated circuit test equipment while the secondary chip is contained within the packaged semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.