Patent assignee · US · COMPANY

Inapac Technology, Inc.

30Patents
6Active
30Granted
41Portfolio score

Filing activity: Sep 21, 2000 → Oct 31, 2007 · 6 expiring within 5 years

Most-cited patents

PatentTitleAreaCited byStatus
US7061263B1 Layout and use of bond pads and probe pads for testing of integrated circuits devices Electricity 54 Expired
US6732304B1 Chip testing within a multi-chip semiconductor package Physics 49 Expired
US6812726B1 Entering test mode and accessing of a packaged semiconductor device Electricity 38 Expired
US6882171B2 Bonding pads for testing of a semiconductor device Electricity 30 Expired
US7133798B1 Monitoring signals between two integrated circuit devices within a single package Electricity 28 Expired
US7265570B2 Integrated circuit testing module Physics 27 Expired
US7444575B2 Architecture and method for testing of an integrated circuit device Physics 27 Expired
US7313740B2 Internally generating patterns for testing in an integrated circuit device Electricity 26 Expired
US7139945B2 Chip testing within a multi-chip semiconductor package Physics 26 Expired
US7466160B2 Shared memory bus architecture for system with processor and memory units Electricity 26 Active
US7006940B1 Set up for a first integrated circuit chip to allow for testing of a co-packaged second integrated circuit chip Electricity 22 Expired
US7307442B2 Integrated circuit test array including test module Physics 21 Active
US7245141B2 Shared bond pad for testing a memory within a packaged semiconductor device Electricity 21 Expired
US7365557B1 Integrated circuit testing module including data generator Physics 20 Expired
US7466603B2 Memory accessing circuit system Physics 20 Active
US7309999B2 Electronic device having an interface supported testing mode Electricity 19 Expired
US7259582B2 Bonding pads for testing of a semiconductor device Electricity 19 Expired
US7310000B2 Integrated circuit testing module including command driver Physics 19 Active
US7404117B2 Component testing and recovery Physics 18 Expired
US7269524B1 Delay lock loop delay adjusting method and apparatus Electricity 17 Active
US7240254B2 Multiple power levels for a chip within a multi-chip semiconductor package Electricity 16 Expired
US7370256B2 Integrated circuit testing module including data compression Physics 16 Expired
US6754866B1 Testing of integrated circuit devices Physics 16 Expired
US7446551B1 Integrated circuit testing module including address generator Physics 15 Expired
US7103815B2 Testing of integrated circuit devices Physics 14 Expired

Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.