Method for making programmable resistance memory element
US6733956B2 · kind B2 · utility
16Cited by
4References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2002 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Jul 7, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable resistance memory element using a conductive sidewall layer as the bottom electrode. The programmable resistance memory material deposited over the top edge of the bottom electrode in a slot-like opening formed in a dielectric material. A method of making the opening using a silylated photoresist.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.