Integrated semiconductor circuit having contact points and configuration having at least two such circuits
US6734474B2 · kind B2 · utility
4Cited by
1References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 23, 2002 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Jul 23, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
For a selection of semiconductor chips stacked on top of one another, the invention includes leading through selection contact points of one chip on a rear side thereof and connecting them to corresponding selection contact points of the other semiconductor chip. Programmable input amplifiers are programmed to be transmissive or blocking through fuses/antifuses so that selection signals applied to the selection contact points either activate or block functional elements only of one or only of the other semiconductor chip. As a result, simple stacking of identically prefabricated semiconductor chips is made possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.