Process for fabricating a capacitor within an integrated circuit, and corresponding integrated circuit
US6734483B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2001 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Aug 17, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76895
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A production of a capacitor includes the simultaneous production, in at least part of an intertrack insulating layer (3) associated with a given metallization level, on the one hand, of the two electrodes (50, 70) and of the dielectric layer (60) of the capacitor and, on the other hand, of a conducting trench (41) which laterally extends the lower electrode of the capacitor, is electrically isolated from the upper electrode and has a transverse dimension smaller than the transverse dimension of the capacitor, and the production, in the interlevel insulating layer (8) covering the intertrack insulating layer, of two conducting pads (80, 81) which come into contact with the upper electrode of the capacitor and with the conducting trench, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.