Semiconductor element and MIM-type capacitor formed in different layers of a semiconductor device
US6734489B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2002 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Apr 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A second-level wire is formed by a dual damascene process in a insulating film. In an upper surface of the first insulating film a metal film is formed and serves as a first electrode of an MIM-type capacitor. A second insulating films has a structure in which a plurality of insulating films are layered on a second interconnection layer, in this order. In a first insulating film of the plurality of insulating films, a second electrode of the MIM-type capacitor is formed. The second electrode has a first metal film formed on a second insulating film of the plurality of the insulating films and a second metal film is formed on the first metal film. A portion of the second insulating film which is sandwiched between the first electrode and the second electrode of the MIM-type capacitor serves as a capacitor dielectric film of the MIM-type capacitor. In the second insulating film, a third-level wire is formed Thus, a semiconductor device and a method of manufacturing the same are provided such that the MIM-type capacitor is formed together with metal wires with no additional complicated step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.