Processor having replay architecture with fast and slow replay paths
US6735688B1 · kind B1 · utility
26Cited by
6References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2000 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Feb 14, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3869
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one aspect of the invention, a microprocessor is provided that includes an execution core, a first replay mechanism and a second replay mechanism. The execution core performs data speculation in executing a first instruction. The first replay mechanism is used to replay the first instruction via a first replay path if an error of a first type is detected which indicates that the data speculation is erroneous. The second replay mechanism is used to replay the first instruction via a second replay path if an error of a second type is detected which indicates that the data speculation is erroneous.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.