Specifying different type generalized event and action pair in a processor
US6735690B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2000 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Jan 28, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/325
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor with a generalized eventpoint architecture, which is scalable for use in a very long instruction word (VLIW) array processor, such as the manifold array (ManArray) processor is described. In one aspect, generalized processor event (p-event) detection facilities are provided by use of compares to check if an instruction address, a data memory address, an instruction, a data value, arithmetic-condition flags, or other processor change of state eventpoint has occurred. In another aspect, generalized processor action (p-action) facilities are provided to cause a change in the program flow by loading the program counter with a new instruction address, generate an interrupt, signal a semaphore, log or count the p-event, time stamp the event, initiate a background operation, or to cause other p-actions to occur. The generalized facilities are defined in the eventpoint architecture as consisting of a control register and three eventpoint parameters, namely at least one register to compare against, a register containing a second compare register, a vector address, or parameter to be passed, and a count or mask register. Based upon this generalized eventpoint architecture, new ca…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.