Method of timing calibration using slower data rate pattern
US6735709B1 · kind B1 · utility
97Cited by
12References
186Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2000 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Mar 9, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved technique and associated apparatus for timing calibration of a logic device is provided. A calibration test pattern is transferred to a logic device first at a data rate slower than normal operating speed to ensure correct capture of the pattern at the device to be calibrated. Once the pattern is correctly captured and stored, the test pattern is transmitted to the logic device at the normal operating data rate to perform timing calibration. The improved technique and apparatus permits the use of any pattern of bits as a calibration test pattern, programmable by the user or using easily-interchangeable hardware.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.