Method for optimizing a cell layout using parameterizable cells and cell configuration data

US6735742B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Joel Hatsch · Holzkirchen, DE
• Winfried Kamp · Munich, DE
• Ronald Kunemund · Dietramszell, DE
• Eva Lackerschmid · Birkenfeld, DE
• Heinz Soldner · Bruckmühl, DE

Key dates

• Filing date: May 24, 2001
• Grant date: May 11, 2004
• Expiry date: Jul 26, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/10
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method for optimizing the layout of cells of an integrated circuit includes providing a cell-based network list with references to cell definitions with parameterizable dimensions, calculating a layout of an integrated circuit using the cell-based network list, extracting a primary network list from the layout, optimizing the component dimensions of at least some of the components of the integrated circuit using at least one predetermined optimization parameter and a simulation using the primary network list, creating an optimized secondary network list using the results of the component optimization, and automatically modifying the layout with respect to cell dimensions using a secondary network list.