Method for fabricating a semiconductor device
US6737288B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2002 |
| Grant date | May 18, 2004 |
| Priority date | — |
| Expiry date | Jun 8, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/30612
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A heterojunction structure has an AlxGa1−xAs layer (0<x≦1), on which an AlyGa1−yAs layer (0≦y≦1 and y<x) is provided and having a band gap energy smaller than that of the AlxGa1−xAs layer and a valence band energy edge higher than that of the AlxGa1−xAs layer. When the AlyGa1−yAs layer is selectively etched, an Au electrode film is formed on a surface of the AlyGa1−yAs layer outside an etching region, a resist pattern is formed covering the Au electrode film and leaving exposed the etching region, and the AlyGa1−yAs layer is selectively removed by etching while irradiating with light, using an etching solution having a Fermi level higher than that of the AlyGa1−yAs layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.