Fabrication method for circuit board
US6740540B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2002 |
| Grant date | May 25, 2004 |
| Priority date | — |
| Expiry date | Nov 29, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49124
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A fabrication method for a circuit board is proposed, wherein a core layer is formed with a plurality of conductive traces, and photo resist is applied on terminals of the conductive traces. A non-solderable material is peelably applied over a support member, and attached to the core layer to cover the conductive traces, wherein adhesion between the support member and the non-solderable material is smaller than adhesion between the non-solderable material and the core layer. Then, the support member is peeled to expose the non-solderable material; further, the non-solderable material is partly removed to expose the photo resist. Finally, the photo resist is etched away to expose the terminals of the conductive traces. The exposed terminals serve as bond pads or fingers where solder balls, bumps or wires are bonded for electrical connection purpose.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.