Integrated semiconductor memory fabrication method

US6740917B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventor

• Peter Beer · Waldshut-Tiengen, DE

Key dates

• Filing date: Jul 15, 2002
• Grant date: May 25, 2004
• Expiry date: Jul 15, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/485

Abstract

In integrated semiconductor memories, the area taken up by a memory cell on a semiconductor substrate is always kept as small as possible to be able to accommodate as many memory cells as possible on the area of the substrate. According to the invention, word or bit lines are disposed as line pairs including two lines running one vertically above the other. As a result, two memory cells can be contact-connected in different substrate depths in a confined space. In each case different memory cells are connected to the upper line of a line pair than to the lower bit line of the same line pair. Semiconductor memories so formed require less substrate area per memory cell.