Ballast resistor with reduced area for ESD protection
US6740936B1 · kind B1 · utility
9Cited by
4References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2002 |
| Grant date | May 25, 2004 |
| Priority date | — |
| Expiry date | May 9, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/43
Abstract
A transistor with ballast resistor formed between the transistor drain and the drain contact is formed by masking regions of the ballast resistor to increase resistivity and thus reduce required area. The invention achieves this without introducing any additional process or masking steps. Thus the invention allows a reduction in IC die size for the same ESD requirement or allows better ESD protection for a given die size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.