Multi-bank memory array architecture utilizing topologically non-uniform blocks of sub-arrays and input/output assignments in an integrated circuit memory device
US6741488B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2002 |
| Grant date | May 25, 2004 |
| Priority date | — |
| Expiry date | Nov 19, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-bank memory array architecture utilizing topologically non-uniform blocks of sub-arrays and input/output (“I/O”) assignments in an integrated circuit memory device. By using non-uniform blocks of multiple identical sub-arrays, non-uniform assignments of blocks to banks and/or non-uniform assignments of I/Os to blocks, it is possible to optimize the dimensions of the chip and the placement of the I/Os with respect to the package pads. In this manner, the granularity of the building blocks of sub-arrays is improved while the flexibility in I/O assignment is also improved leading to more efficient and flexible chip layouts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.