Data memory with a plurality of memory banks

US6741513B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Heinz Honigschmid · Starnberg, DE
• Gerhard Muller · Grafing, DE

Key dates

• Filing date: Nov 2, 2001
• Grant date: May 25, 2004
• Expiry date: Nov 2, 2021

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C8/12
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

The data memory has a plurality of banks, each with a multiplicity of memory cells that form a matrix of rows and columns with respectively assigned matrix row lines and column lines. The banks are arranged spatially one on top of the other as stacks, with the stack edges that are parallel to the matrix rows and at which the ends of the column lines that are connected to a respective column-driving device are located, lie in a common plane. The common plane extends in the direction of the matrix rows and is substantially orthogonal with respect to the direction of the columns. The column-driving devices of all the banks are arranged directly adjacent to one another as a block in the direction of the columns, on or near the same edge of the bank stack. The banks preferably contain memory cells which can be read out without damage, and in each case a plurality of column lines are each assigned to one common sense amplifier in the column-driving device of each bank.