Thermal annealing process for producing low defect density single crystal silicon
US6743289B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2002 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Feb 11, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/2822
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A thermal annealing process for producing a low defect density single crystal silicon wafer. The process includes thermally annealing a wafer having a first axially symmetric region which extends radially inwardly from the circumferential edge, contains silicon self-interstitials as the predominant intrinsic point defect and is substantially free of agglomerated interstitial defects and a second axially symmetric region which has vacancies as the predominant intrinsic point defect. The wafer is subjected to a thermal anneal at a temperature in excess of about 1000° C. in an atmosphere of hydrogen, argon or a mixture thereof to dissolve agglomerated vacancy defects present in the second axially symmetric region within a layer extending from the front side toward the central plane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.