Method of fabricating a CMOS device with integrated super-steep retrograde twin wells using double selective epitaxial growth
US6743291B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2002 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Jan 2, 2023 |
Classification
- Technology area (CPC C)Chemistry; Metallurgy
- CPC primaryC30B25/20
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A process of fabricating a CMOS device comprised with super-steep retrograde (SSR), twin well regions, has been developed. The process features the use of two, selective epitaxial growth (SEG), procedures, with the first SEG procedure resulting in the growth of bottom silicon shapes in the PMOS, as well as in the NMOS region of the CMOS device. After implantation of the ions needed for the twin well regions, into the bottom silicon shapes, a second SEG procedure is employed resulting in growth of top silicon shapes on the underlying, implanted bottom silicon shapes. An anneal procedure then distributes the implanted ions resulting in an SSR N well region in the composite silicon shape located in the PMOS region, and resulting in an SSR P well region in the composite silicon shape located in the NMOS region of the CMOS device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.