Wenhe Lin
28Patents
12h-index
34Co-inventors
77Inventor score
Filing activity: Sep 27, 2000 → Feb 22, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6743291B2 | Method of fabricating a CMOS device with integrated super-steep retrograde twin wells using double selective epitaxial growth | Chemistry; Metallurgy | 122 | Expired |
| US6475908B1 | Dual metal gate process: metals and their silicides | Electricity | 62 | Expired |
| US6664156B1 | Method for forming L-shaped spacers with precise width control | Electricity | 56 | Expired |
| US6458695B1 | Methods to form dual metal gates by incorporating metals and their conductive oxides | Electricity | 46 | Expired |
| US6486080B2 | Method to form zirconium oxide and hafnium oxide for high dielectric constant materials | Electricity | 32 | Expired |
| US6709912B1 | Dual Si-Ge polysilicon gate with different Ge concentrations for CMOS device optimization | Emerging Cross-Sectional Technologies | 28 | Expired |
| US6750519B2 | Dual metal gate process: metals and their silicides | Electricity | 25 | Expired |
| US6670248B1 | Triple gate oxide process with high-k gate dielectric | Electricity | 20 | Expired |
| US6534388B1 | Method to reduce variation in LDD series resistance | Electricity | 16 | Expired |
| US6403425B1 | Dual gate oxide process with reduced thermal distribution of thin-gate channel implant profiles due to thick-gate oxide | Electricity | 14 | Expired |
| US7005716B2 | Dual metal gate process: metals and their silicides | Electricity | 13 | Expired |
| US7256084B2 | Composite stress spacer | Electricity | 12 | Expired |
| US7445978B2 | Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS | Electricity | 11 | Expired |
| US6677652B2 | Methods to form dual metal gates by incorporating metals and their conductive oxides | Electricity | 10 | Expired |
| US6524910B1 | Method of forming dual thickness gate dielectric structures via use of silicon nitride layers | Electricity | 8 | Expired |
| US6891233B2 | Methods to form dual metal gates by incorporating metals and their conductive oxides | Electricity | 8 | Expired |
| US8624329B2 | Spacer-less low-K dielectric processes | Electricity | 5 | Active |
| US6835989B2 | Methods to form dual metal gates by incorporating metals and their conductive oxides | Electricity | 5 | Expired |
| US7999325B2 | Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS | Electricity | 3 | Active |
| US7977185B2 | Method and apparatus for post silicide spacer removal | Electricity | 3 | Expired |
| US7993997B2 | Poly profile engineering to modulate spacer induced stress for device enhancement | Electricity | 3 | Active |
| US7615427B2 | Spacer-less low-k dielectric processes | Electricity | 3 | Active |
| US8148221B2 | Double anneal with improved reliability for dual contact etch stop liner scheme | Electricity | 3 | Active |
| US7022625B2 | Method of fabricating a gate dielectric layer with reduced gate tunnelling current and reduced boron penetration | Electricity | 2 | Expired |
| US7615433B2 | Double anneal with improved reliability for dual contact etch stop liner scheme | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.