Method of fabricating an integrated circuit package utilizing an interposer surrounded by a flexible dielectric material with conductive posts
US6743661B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 17, 2002 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Sep 17, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49171
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for flexibly bonding an integrated circuit package to a printed circuit board are provided. The apparatus includes a semiconductor having first and second sides, where the first side defines an inner region and peripheral region. The inner region is surrounded by the peripheral region. An interposer having a substantially similar coefficient of thermal expansion to the semiconductor is included. A dielectric region surrounding the interposer is included. The dielectric region is configured to be partially elastic. A plurality of posts extends transversely through the dielectric region. The post have first and second ends where the first end is configured to be attached to the peripheral region of the semiconductor chip. The second ends of the posts are configured to be attached to an external assembly, wherein the posts are able to absorb stress due to a thermal expansion mismatch between the external assembly and the interposer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.