Method of forming a semiconductor array of floating gate memory cells and strap regions, and a memory array and strap regions made thereby
US6743674B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 24, 2002 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Jul 24, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, along with strap regions interlaced within the array. The array includes word lines and source lines that connect together control gates and source regions from memory cells contained in row within the array. The strap regions include word line strap cells through which the word lines traverse, wherein the word lines completely traverse across the strap regions, and source line strap cells in which the source lines terminate without completely traversing across the strap region. The control gate polysilicon is formed over the substrate, and protected by a layer of protective material, before the formation of other polysilicon elements associated with the memory array, to ensure the proper remove of residual polysilicon stringers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.