Circuit for fast and accurate memory read operations
US6744674B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2003 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Mar 13, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit senses current in a target cell during a read operation. According to one exemplary embodiment, the memory circuit comprises the target cell, a first neighboring cell, and an operational amplifier. The first target cell has a first bit line connected to ground; the target cell also has a second bit line connected to a drain voltage. A sensing circuit is coupled at a first node to at least one of the first bit line or the second bit line. The first neighboring cell has a third bit line connected to a second node. The operational amplifier has an output terminal connected at the second node to the third bit line. The operational amplifier has a noninverting input terminal connected to said first node, and also has an inverting input terminal connected to the second node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.