Semiconductor memory device with mode register and method for controlling deep power down mode therein
US6744687B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2002 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Feb 8, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are a semiconductor memory device with a mode register that prevents the semiconductor device from undesirably entering into a deep power down mode during the beginning of a power up and a method for controlling a deep power down mode therein. An internal power supply voltage generator generates an internal power supply voltage of the semiconductor memory device. A clock buffer buffers external clock and clock enable signals to generate internal clock and clock enable signals. A command decoder generates an intermediate deep power down mode entry signal or a mode register setting signal. A mode register setting latch circuit latches the mode register setting signal from the command decoder. A deep power down mode controller generates a final deep power down mode entry signal. A semiconductor memory device is accordingly prevented from undesirably entering into a deep power down mode during beginning of a power up.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.