Oxygen barrier for cell container process
US6746930B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2001 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | Oct 14, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory cell container of a DRAM semiconductor memory device and method for manufacturing the cell container are disclosed. The cell includes a container formed in a structural layer such as borophosphosilicate glass. The container is then lined with a polysilicon such as hemispherical grained polysilicon. A dielectric layer is deposited over the polysilicon layer. A barrier layer is deposited over the dielectric layer such that the opening of the container is covered but not the sidewalls or the bottom of the container. The cell is then oxidized and the barrier layer provides protection as an oxygen barrier during the oxidation or any following re-oxidation process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.