Microprocessor reservation mechanism for a hashed address system
US6748501B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2000 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | Jun 12, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0855
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of storing values in a sliced cache by providing separate, but coordinated, reservation units for each cache slice. When a load-with-reserve (larx) operation is issued from the processor core as part of an atomic read-modify-write sequence, a message is broadcast to each of the cache slices to clear reservation flags in the slices; a reservation flag is also set in the target cache slice, and a memory address associated with the load-with-reserve operation is loaded into a reservation unit of the target cache slice. When a conditional store operation is issued from the core to complete the atomic read-modify-write sequence, a second message is broadcast to any non-target cache slice of the processing unit to clear reservation flags in the non-target cache slice(s). The conditional store operation passes if the reservation flag of the target cache slice is still set, and the memory address associated with the conditional store operation matches the memory address loaded in a reservation unit of the target cache slice. The broadcast messages coordinate the reservation units and facilitate the use of larger sliced caches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.