Method for making programmable resistance memory element
US6750079B2 · kind B2 · utility
157Cited by
5References
42Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2001 |
| Grant date | Jun 15, 2004 |
| Priority date | — |
| Expiry date | Jun 26, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of making an electrically operated programmable resistance memory element. A sidewall spacer is used as a mask to form raised portions on an edge of a conductive sidewall layer. The modified conductive sidewall layer is used as an electrode for the memory element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.