Integrated semiconductor memory and fabrication method

US6750098B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Till Schlosser · Dresden, DE
• Dirk Manger · Dresden, DE

Key dates

• Filing date: Jul 15, 2003
• Grant date: Jun 15, 2004
• Expiry date: Jul 15, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/485

Abstract

In semiconductor memories having a surrounding gate configuration, webs, i.e. vertical rectangular pillars made of substrate material, are formed at the surface of a semiconductor substrate and are surrounded by the gate electrodes in a lower region. Conventionally, it is not possible for word lines to make contact with the gate electrodes in the lower region of the webs without at the same time electrically influencing substrate regions at a higher level in the webs or short-circuiting bit lines from their sidewalls, unless complicated methods requiring additional lithography steps are used. A method for the self-aligning, selective contact-connection of the peripheral gate electrodes is performed with the aid of an insulation layer having a smaller layer thickness than the peripheral gate electrodes.