Dirk Manger
30Patents
8h-index
64Co-inventors
74Inventor score
Filing activity: Dec 27, 1999 → Dec 19, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7915667B2 | Integrated circuits having a contact region and methods for manufacturing the same | Electricity | 467 | Active |
| US7109544B2 | Architecture for vertical transistor cells and transistor-controlled memory cells | Electricity | 105 | Expired |
| US7005240B2 | Method for forming a hard mask in a layer on a planar device | Electricity | 35 | Expired |
| US7368752B2 | DRAM memory cell | Electricity | 23 | Expired |
| US6261951A | Plasma treatment to enhance inorganic dielectric adhesion to copper | Electricity | 17 | Expired |
| US7649779B2 | Integrated circuits; methods for manufacturing an integrated circuit; memory modules; computing systems | Electricity | 12 | Active |
| US7662721B2 | Hard mask layer stack and a method of patterning | Electricity | 11 | Active |
| US6919255B2 | Semiconductor trench structure | Electricity | 10 | Expired |
| US7074660B2 | FinFet device and method of fabrication | Electricity | 8 | Expired |
| US6593660B2 | Plasma treatment to enhance inorganic dielectric adhesion to copper | Electricity | 6 | Expired |
| US6932916B2 | Semiconductor substrate with trenches of varying depth | Electricity | 5 | Expired |
| US7678679B2 | Vertical device with sidewall spacer, methods of forming sidewall spacers and field effect transistors, and patterning method | Electricity | 4 | Active |
| US6750098B2 | Integrated semiconductor memory and fabrication method | Electricity | 4 | Expired |
| US7141845B2 | DRAM cell array and memory cell arrangement having vertical memory cells and methods for fabricating the same | Electricity | 4 | Expired |
| US7005346B2 | Method for producing a memory cell of a memory cell field in a semiconductor memory | Electricity | 3 | Expired |
| US6861688B2 | Line configuration for bit lines for contact-connecting at least one memory cell, semiconductor component with a line configuration and method for fabricating a line configuration | Electricity | 2 | Expired |
| US7737049B2 | Method for forming a structure on a substrate and device | Electricity | 2 | Active |
| US7473952B2 | Memory cell array and method of manufacturing the same | Electricity | 2 | Expired |
| US6956260B2 | Integrated semiconductor memory with wordlines conductively connected to one another in pairs | Electricity | 2 | Expired |
| US9812369B2 | BiMOS device with a fully self-aligned emitter-silicon and method for manufacturing the same | Electricity | 1 | Active |
| US7863149B2 | Method for fabricating a capacitor | Electricity | 1 | Expired |
| US7829892B2 | Integrated circuit including a gate electrode | Electricity | 1 | Active |
| US7825031B2 | Method of fabricating a semiconductor device | Electricity | 1 | Active |
| US10020387B2 | Method for manufacturing a bipolar junction transistor | Electricity | 1 | Active |
| US10164086B2 | Vertical field effect transistor device having alternating drift regions and compensation regions | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.