Thermally enhanced semiconductor build-up package
US6750397B2 · kind B2 · utility
13Cited by
5References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2002 |
| Grant date | Jun 15, 2004 |
| Priority date | — |
| Expiry date | Feb 15, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor build-up package includes a die, a metal carrier, and a plurality of dielectric layers. The metal carrier has a surface with a cavity for supporting the die. The surface of metal carrier is coplanar to the active surface of die for building up a plurality of dielectric layers. Each dielectric layer has metal columns for inner electrical connection. The metal carrier covers passive surface and sides of the die with a larger area for heat dissipating, so the heat generated from the die is dissipated fast through the metal carrier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.