System and method for charge restoration in a non-volatile memory device
US6751146B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2003 |
| Grant date | Jun 15, 2004 |
| Priority date | — |
| Expiry date | Jan 7, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device comprising logic for charge restoration. The restore logic controls a read circuit for determining a value associated with the threshold voltage of a memory cell selected from a memory cell array, and compares the value to one or more boundary values to determine whether or not the memory cell value is out of bounds. In the event that the memory cell value is out of bounds, a target value for the memory cell is established. The restore logic controls a write circuit that applies a write pulse to the memory cell. The read and write process is repeated as necessary until the target value for the memory cell is achieved. The restore logic may include a processor for performing a statistical analysis on the memory cell array in order to determine target restoration values. Memory cells within the array may be reserved for use by the restore logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.