Memory device operable in either a high-power, full-page size mode or a low-power, reduced-page size mode
US6751159B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2001 |
| Grant date | Jun 15, 2004 |
| Priority date | — |
| Expiry date | Feb 28, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes 4 memory banks each of which includes first and second arrays of memory cells. A mode register is programmed with a bit that selects a high-power, large-page operating mode or a low-power, small-page operating mode. In the high-power mode, a row decoder is coupled to the row lines in both the first and second arrays. In the low-power mode, the row decoder is coupled to the row lines in only one of the arrays as determined by the state of an array select signal. The array select signal corresponds to the most significant bit of the column address, but it is applied to the memory device at the time the row address is applied to the memory device. Sense amplifiers coupled to the first and second arrays may also be selectively enabled when the row lines for the corresponding array are coupled to the row decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.