Method for fabricating flash memory cell
US6753223B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 15, 2002 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Nov 15, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A method for fabricating a flash memory cell. The method starts with sequential formation of a first insulating layer, a first conductive layer and pad layer on a semiconductor substrate. Part of the pad layer is removed to form a first opening, followed by forming a conductive spacer, i.e. the tip, on the sidewalls of the first opening. Then, parts of the pad layer, first conductive layer, first insulating layer and substrate are removed to form a second opening. Next, a second insulating layer is formed to fill the first opening and the second opening to form a first gate insulating layer and shallow trench isolation. The first gate insulating layer is used as hard mask to remove part of the first conductive layer and the first insulating layer to form a floating gate and a second insulating layer. Tunneling oxide and control gate are then formed on the floating gate. Finally, a source/drain is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.