Method for planarizing an isolating layer
US6753236B2 · kind B2 · utility
2Cited by
8References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2002 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Sep 3, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for planarizing the surface of an isolating layer that is deposited on a semiconductor body is described. Zones where the isolating layer has a low level are covered with a block mask in order to be able to selectively etch zones of the isolating layer with a higher level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.