Composite etching stop in semiconductor process integration
US6753260B1 · kind B1 · utility
11Cited by
15References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2001 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Jan 10, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76807
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A new method of forming a composite etching stop layer is described. An etching stop layer is deposited on a substrate wherein the etching stop layer is selected from the group consisting of: silicon carbide, silicon nitride, SiCN, SiOC, and SiOCN. A TEOS oxide layer is deposited by plasma-enhanced chemical vapor deposition overlying the etching stop layer. The composite etching stop layer has improved moisture resistance, better etching selectivity, and lower dielectric constant than other etching stop layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.