Patent · US Expired

Evaluation circuit for a DRAM

US6754110B2 · kind B2 · utility

2Cited by

3References

7Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Peter Beer · Waldshut-Tiengen, DE
Thilo Schaffroth · Weingarten, DE

Key dates

Filing date	Jul 8, 2002
Grant date	Jun 22, 2004
Priority date	—
Expiry date	Jul 23, 2022

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/4097
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A circuit configuration for evaluating electrical charges of memory cells in a DRAM is provided. Signal lines within the evaluation circuit cross one another in order to reduce parasitic coupling capacitances between adjacent signal lines of a memory cell array.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.