Topography correction for testing of redundant array elements
US6754113B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2002 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Sep 24, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data topography correction circuit for a semiconductor memory device and method for testing the device is provided. The data topography correction circuit includes a redundant hit circuit for determining if a redundant element has been used to replace a defective element; and a redundant topology correction scrambler circuit for converting data from a data topology of the defective element to a data topology of the redundant element. The method includes the steps of providing an address of a memory array element of the device to be tested; determining if the memory array element has been replaced with a redundant element; and, if the memory array element has been replaced, correcting test data to the data topology of the redundant element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.