Memory array with read/write methods
US6754746B1 · kind B1 · utility
435Cited by
140References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2000 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Mar 23, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Improved circuitry for connecting the memory array to a data bus allows for high speed accessing of the memory array. Sense amplifier latches are coupled to each column of memory cells. The latched sense amplifiers are coupled to decoders which, in turn, are coupled to data amplifiers. The data amplifiers are coupled to a data bus. Data being read from or written to the memory cells is via the sense amplifier latches, the decoders, and data amplifiers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.