Semiconductor memory array of floating gate memory cells with horizontally oriented floating gate edges
US6756633B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2002 |
| Grant date | Jun 29, 2004 |
| Priority date | — |
| Expiry date | Jun 25, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6891
Abstract
A self aligned method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The drain region is formed underneath the trench. An electrically conductive floating gate is formed over and insulated from a portion of the channel region, with a horizontally oriented edge extending therefrom. An electrically conductive control gate is formed having a first portion disposed in the trench and a second portion disposed adjacent to and insulated from the floating gate edge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.