Use of sic for preventing copper contamination of low-k dielectric layers
US6756672B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2001 |
| Grant date | Jun 29, 2004 |
| Priority date | — |
| Expiry date | Jun 13, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization level. The first etch stop layer is disposed over the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The via can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the via, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer can be formed from silicon carbide. A method of manufacturing the semiconductor device is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.