DQS postamble noise suppression by forcing a minimum pulse length
US6760261B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2002 |
| Grant date | Jul 6, 2004 |
| Priority date | — |
| Expiry date | Sep 25, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and method for suppressing the effect of noise on a data strobe signal DQS in a double data rate (DDR) SDRAM is provided. The circuit includes a data input latch circuit for receiving data to be stored and for latching the data in a memory array in response to a control signal; and a control signal generator for generating the control signal in response to a data strobe signal wherein the control signal has a predetermined minimum pulse width of the data strobe signal. The control signal generator includes a reset/set flip-flop for generating the control signal, wherein the flip-flop is set by the data strobe signal; and a low pass filter for receiving the data strobe signal and for outputting a reset signal to the flip-flop if the data strobe signal is greater than the predetermined minimum pulse width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.