Buffer circuit for a peripheral interface circuit in an I/O node of a computer system
US6760791B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 7, 2002 |
| Grant date | Jul 6, 2004 |
| Priority date | — |
| Expiry date | Jan 17, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/128
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A buffer circuit for a peripheral interface circuit in an I/O node of a computer system. A buffer circuit includes a first buffer and a second buffer. The first buffer may be configured to store a plurality of selected packet commands within a plurality of storage locations. The second buffer is coupled to the first buffer and may be configured to store a plurality of index values. Each index value corresponds to one of the storage locations in the first buffer. The buffer circuit further includes a write logic circuit that is coupled between the first buffer and the second buffer. The write logic circuit may be configured to successively read each of the plurality of index values from the second buffer and to cause a selected packet command to be stored in each storage location corresponding to each of the plurality of index values within the first buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.